Input

Input now working.
Still buggy. Presses remain unstable.
Needs either buffer capacitors, readout redundancy in software or both.

1 files changed, 103 insertions, 77 deletions

diff --git a/Software/pinlock.asm b/Software/pinlock.asm
index e2204bf..84d4dd7 100644
--- a/Software/pinlock.asm
+++ b/Software/pinlock.asm
@@ -21,8 +21,11 @@ init:
 	out DDRA, tmp0
 	ldi tmp0, 0b11111111
 	out DDRB, tmp0
-	ldi tmp0, 0b11101100
+	ldi tmp0, 0b11101110
 	out DDRD, tmp0
+	cbi PORTC, 0
+	sbi DDRC, 0
+	sbi DDRC, 1
 	ldi tmp0, 0b00000000
 	out PORTD, tmp0
 	ldi heart, 0
@@ -38,10 +41,6 @@ init:
 	ldi par0, 3
 	ldi par1, 3
 	rcall display
-	ldi par0, 0xFF
-	rcall status
-stop:
-	rjmp stop
 	rjmp main
 
 debug_heart:
@@ -64,7 +63,6 @@ debug_heart:
 	ret
 
 main:
-	rcall debug_heart
 	rcall input
 	mov par1, ret0
 	lsr par1
@@ -88,6 +86,7 @@ main:
 	andi par1, 0x0F
 	ldi par0, 3
 	rcall display
+	;rcall debug_heart
 	rjmp main
 
 wait:
@@ -122,7 +121,7 @@ shift_out:
 	push tmp0
 	ldi tmp0, 8
 shift_out_loop:
-	sbrs par0, 0
+	sbrs par0, 7
 	rjmp shift_out_low
 	rjmp shift_out_high
 shift_out_low:
@@ -136,7 +135,7 @@ shift_out_high:
 	icall
 	rjmp shift_out_end
 shift_out_end:
-	lsr par0
+	lsl par0
 	dec tmp0
 	brne shift_out_loop
 	pop tmp0
@@ -155,22 +154,13 @@ shift_in:
 	ldi ret0, 0
 shift_in_loop:
 	lsl ret0
-	mov r31, par0
-	mov r30, par1
-	icall
 	mov r31, par2
 	mov r30, par3
 	icall
-	cpi ret2, 0
-	breq shift_in_low
-	rjmp shift_in_high
-shift_in_low:
-	cbr ret0, 0
-	rjmp shift_in_end
-shift_in_high:
-	sbr ret0, 0
-	rjmp shift_in_end
-shift_in_end:
+	or ret0, ret2
+	mov r31, par0
+	mov r30, par1
+	icall
 	dec tmp0
 	brne shift_in_loop
 	pop tmp0
@@ -288,34 +278,31 @@ input_loop:
 	rcall shift_out
 	rjmp input_read
 input_write_low:
-	push tmp0
-	in tmp0, PORTD
-	cbr tmp0, 3
-	cbr tmp0, 5
-	out PORTD, tmp0
-	sbr tmp0, 5
-	out PORTD, tmp0
-	pop tmp0
+	cbi PORTD, 3
+	rcall input_write_clk
 	ret
 input_write_high:
-	push tmp0
-	in tmp0, PORTD
-	sbr tmp0, 3
-	cbr tmp0, 5
-	out PORTD, tmp0
-	sbr tmp0, 5
-	out PORTD, tmp0
-	pop tmp0
+	sbi PORTD, 3
+	rcall input_write_clk
 	ret
 input_read:
+	; load
 	push tmp0
-	in tmp0, PORTD
-	sbr tmp0, 2
-	out PORTD, tmp0
-	cbr tmp0, 2
-	out PORTD, tmp0
-	sbr tmp0, 2
-	out PORTD, tmp0
+	sbi PORTD, 2
+	cbi PORTD, 2
+	push par0
+	push par1
+	push par2
+	ldi par0, 1
+	ldi par1, 1
+	ldi par2, 1
+	rcall wait
+	pop par2
+	pop par1
+	pop par0
+	rcall input_read_clk
+	sbi PORTD, 2
+	; shift in
 	push par0
 	ldi par0, HIGH(input_read_clk)
 	ldi par1, LOW(input_read_clk)
@@ -326,63 +313,102 @@ input_read:
 	mov tmp0, ret0
 	pop ret0
 	pop par0
+	;lsr tmp0
+	;lsr tmp0
+	;lsr tmp0
+	;lsr tmp0
 	; par0 = row
 	; tmp0 = col
-	mov tmp1, par0
-	andi tmp1, 0x03
-	cpi tmp1, 0
-	breq input_read_rows_01
-	mov tmp1, par0
-	lsr tmp1
-	lsr tmp1
-	rjmp input_read_rows_23
+	sbrc par0, 0
+	rjmp input_read_row_0
+	sbrc par0, 1
+	rjmp input_read_row_1
+	sbrc par0, 2
+	rjmp input_read_row_2
+	sbrc par0, 3
+	rjmp input_read_row_3
+input_write_clk:
+	cbi PORTC, 1
+	push par0
+	push par1
+	push par2
+	ldi par0, 1
+	ldi par1, 1
+	ldi par2, 1
+	rcall wait
+	sbi PORTC, 1
+	ldi par0, 1
+	ldi par1, 1
+	ldi par2, 1
+	rcall wait
+	pop par2
+	pop par1
+	pop par0
+	ret
 input_read_clk:
-	push tmp1
-	in tmp1, PORTD
-	cbr tmp1, 5
-	out PORTD, tmp1
-	sbr tmp1, 5
-	out PORTD, tmp1
-	pop tmp1
+	cbi PORTD, 5
+	push par0
+	push par1
+	push par2
+	ldi par0, 1
+	ldi par1, 1
+	ldi par2, 1
+	rcall wait
+	sbi PORTD, 5
+	ldi par0, 1
+	ldi par1, 1
+	ldi par2, 1
+	rcall wait
+	pop par2
+	pop par1
+	pop par0
 	ret
 input_read_bit:
-	in ret2, PORTD
-	andi ret2, 0b00010000
+	ldi ret2, 0
+	sbic PIND, 4
+	ldi ret2, 1
+	;
+	;cpi ret2, 0
+	;breq debug_dsp
+	;push par0
+	;push par1
+	;ldi par0, 0
+	;ldi par1, 1
+	;rcall display
+	;pop par1
+	;pop par0
 	ret
-input_read_rows_01:
-	andi tmp1, 1
-	cpi tmp1, 1
-	breq input_read_row_0
-	rjmp input_read_row_1
+;debug_dsp:
+	;push par0
+	;push par1
+	;ldi par0, 0
+	;ldi par1, 7
+	;rcall display
+	;pop par1
+	;pop par0
+	;ret
 input_read_row_0:
 	andi ret0, 0xF0
-	rjmp input_read_rows_01_end
+	or ret0, tmp0
+	rjmp input_end
 input_read_row_1:
 	andi ret0, 0x0F
 	lsl tmp0
 	lsl tmp0
 	lsl tmp0
 	lsl tmp0
-	rjmp input_read_rows_01_end
-input_read_rows_01_end:
 	or ret0, tmp0
 	rjmp input_end
-input_read_rows_23:
-	andi tmp1, 1
-	cpi tmp1, 1
-	breq input_read_row_2
-	rjmp input_read_row_3
 input_read_row_2:
 	andi ret1, 0xF0
-	rjmp input_read_rows_23_end
+	or ret1, tmp0
+	rjmp input_end
 input_read_row_3:
 	andi ret1, 0x0F
 	lsl tmp0
 	lsl tmp0
 	lsl tmp0
 	lsl tmp0
-	rjmp input_read_rows_23_end
-input_read_rows_23_end:
 	or ret1, tmp0
 	rjmp input_end
 input_end: