summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-09-08StatesLeonard Kugis
Added failed output.
2020-09-08EEPROMLeonard Kugis
State machine finished. EEPROM io working.
2020-09-05SoftwareLeonard Kugis
General mechanism working. Needs refinement with EEPROM store/load.
2020-09-04Input, HandlerLeonard Kugis
Reworked display function. Input fully working. Implemented basic entry handler.
2020-09-03InputLeonard Kugis
Moved old state to test.
2020-09-03InputLeonard Kugis
Readout bits not negated. Manual clearing of input shift register.
2020-09-02InputLeonard Kugis
Input now working. Still buggy. Presses remain unstable. Needs either buffer capacitors, readout redundancy in software or both.
2020-09-01inputLeonard Kugis
finished input completely buggy
2020-08-31Merge branch 'master' of collaborating.tuhh.de:cev7691/pinlockLeonard Kugis
2020-08-31Updated gitignoreLeonard Kugis
2020-08-28SoftwareLeonard Kugis
Implemented display function.
2020-08-28SoftwareLeonard Kugis
Implemented basic functionality.
2020-07-28Restructured foldersLeonard Kugis
2020-06-21GeneralLeonard Kugis
Added real world units for capacitors and resistors.
2020-02-04Finished PCBLeonard Kugis
2020-02-04Optimized layoutLeonard Kugis
2020-02-04Merge branch 'master' of collaborating.tuhh.de:cev7691/pinlockLeonard Kugis
2020-02-04LayoutLeonard Kugis
Optimizations. Changed packaging of some parts.
2020-01-23CrystalLeonard Kugis
Replaced crystal with available ABM3B.
2020-01-03GeneralLeonard Kugis
Fixed incorrect displays not matching.
2019-11-25Merge branch 'master' of collaborating.tuhh.de:cev7691/pinlockLeonard Kugis
2019-11-25filled groundLeonard Kugis
2019-11-25FreeroutingLeonard Kugis
2019-11-25LayoutLeonard Kugis
Placement corrections.
2019-11-25Larger pin headersLeonard Kugis
2019-11-25.gitignoreLeonard Kugis
Added fabrication outputs to gitignore.
2019-11-25LayoutLeonard Kugis
Added ground plane.
2019-11-25FreeroutingLeonard Kugis
2019-11-25Schematic, LayoutLeonard Kugis
Changed Barrel Jack pinout. Layout components placed.
2019-11-24Layout not fitting yet, needs improvementLeonard Kugis
2019-11-24Begin associationsLeonard Kugis
2019-11-24GeneralLeonard Kugis
Added references to all elements.
2019-11-21Begin renamingLeonard Kugis
2019-11-20UARTLeonard Kugis
Changed UART from 2 to 4 pin connector, connecting GND and VCC additionally.
2019-11-19GeneralLeonard Kugis
Removed too many test points.
2019-11-13.Leonard Kugis
2019-11-13Schematic, mainLeonard Kugis
Added capacitors for subschematics.
2019-11-13Schematic, generalLeonard Kugis
Added test points everywhere neccessary. Added missing pull resistors to guarantee a defined state everywhere.
2019-11-13Schematic, UARTLeonard Kugis
Added connectors for UART access.
2019-11-13Schematic, mainLeonard Kugis
Added pull resistors to every pin of uC. Restructured main schematic. Added ISP interface.
2019-11-13Schematic, mainLeonard Kugis
Added capacitor in parallel to reset switch to reduce sensitivity and oscillations.
2019-11-13Schematic, main, generalLeonard Kugis
Added pull resistors to all ports. Added capacitors for all components to prevent high switching currents. Reordered status LEDs and transistors.
2019-11-07Schematic, StatusLeonard Kugis
Separated logic IO from power with transistors.
2019-11-07Schematic, JTAGLeonard Kugis
Added JTAG interface.
2019-11-07Removed untracked filesLeonard Kugis
2019-11-07Added .gitignoreLeonard Kugis
2019-11-07Schematic, PinoutLeonard Kugis
Moved buttons and status interface to Port D to prepare Port C as JTAG interface.
2019-11-04Add README.mdLeonard Kugis
2019-11-04Add LICENSELeonard Kugis
2019-11-04LayoutLeonard Kugis
Minor layout fix.
generated by cgit v1.2.1 (git 2.18.0) at 2024-09-20 08:27:30 +0000